搜索资源列表
pcm_verilog
- 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
hamin0132
- 汉明码的编结码模块，用verilog写成，为Modelsim下的一个工程。-series guitar code modules, using Verilog languages, as Modelsim of a project.
crc3321
- CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
uart_test_Verilog
- 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configura
CPU-Pipeline
- 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
rom_test
- 基于SPARTAN6 的ROM读写内容，Verilog语言，完整工程(SPARTAN6 based ROM reading and writing content, Verilog language, complete engineering)
C5G_LPDDR2_RTL_Test
- LPDDR2工程，alteral的c5芯片，板子上验证过，可以直接用。(LPDDR2 project, alteral's C5 chip, has been verified on board and can be directly used.)
at7_ex04
- 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
C5G_SRAM_RTL_Test
- 官网c5板子的SRAM工程，可以直接一直使用。(The SRAM project of official website C5 board can be used directly)
mips16
- 来自openhec平台，完整的mips16cpu设计。未添加工程，需自己手动建立工程添加文件，仅供参考。(mips16 cpu.no vivado project.It's just for teaching.If you want to learn more about it, please search for OpenHec.)
fpga_slavefifo2b_verilog
- fpga控制USB接口数据收发，包含verilog 仿真代码和调试工程(fpga control usb3.0, modelsim simulation, verilog language)
electrical lock
- 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
Verilog
- 01-08例程为数电基础部分：比较简单，代码中可明显看出或是有中文注释，或是在工程代码主文件最前面有文字注释说明。(The 01-08 routine is the basic part of the digital power: it is relatively simple. It can be clearly seen in the code or have Chinese annotations, or in the front of the master code of the eng
TLT_drive
- 关于彩屏（TLT）驱动的编写，实现彩屏的显示，工程在quartus13中建立，包括了仿真设计(About the color screen (TLT) driver's preparation, the realization of the color display, the project was established in quartus13, including the simulation design.)
TwoOderPll
- 1、资料包含二阶环路设计简要说明，Matlab程序，Matlab程序模拟FPGA工作方式，对各变量进行了量化处理 2、资料包含使用Vivado2015.4.2版本的工程文件，可直接运行查看仿真结果 3、参考资料为杜勇老师的《锁相环技术原理及其FPGA实现》(1. The data include a brief descr iption of the second-order loop design. The MATLAB program and the MATLAB program sim
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve
Bayer2RGB
- Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
VerilogUart_Modelsim
- 使用Verilog编写的UART ，用Modelsim仿真工程。(use Verilog Write UART Program, Modelsim simmulate the project)
drsstc
- 实现SKP/PDM功能的drsstc工程文件(DRSSTC project file for SKP / PDM)
AM调制解调
- 基于Artix-7 FPGA的AM调制解调代码，从AD读入信号后，进行AM调制，并解调输出（将代码分成两个工程就是AM的调制和解调），其中解调用到的数字滤波采用MATLAB设计(The AM modulation and demodulation code based on artix-7 FPGA, after reading the signal from AD, carries out AM modulation, and demodulates the output (the code